Method and device for echo cancelling

ABSTRACT

Echo cancelling in a communication line system, particularly an ISDN or XDSL system, is performed by means of a tunable hybrid ( 5 ) which comprises tunable passive elements and is integrated in the analog part of the front end ( 3 ), whereby the values of the tunable passive elements are controlled by digital control means ( 4 ), for example a microprocessor.

[0001] The invention concerns a method for echo cancelling in a communication line system, particularly an integrated services digital network, abbreviated with ISDN, or any digital subscriber line , abbreviated with XDSL, system. Echo cancelling is normally performed in the analog front end of the communication line system, more particularly in between the line transformer and the analog/digital and digital/analog converters. The analog front end is part of the interface between the two-wire line and the digital transmitting and receiving devices coupled to it. It is known to realise echo cancelling by means of digital filter techniques.

[0002] Another known method consists in the synthesis of a digital hybrid impedance at the digital side of the A/D converter.

[0003] U.S. Pat. No. 5,287,406 discloses such method. A digital balancing circuit for cancelling a return echo is operatively connected to the two-wire/four-wire conversion means.

[0004] These digital methods for echo cancelling can however not sufficiently remove inherent non-linear distortion originating within the analog front end itself in the RX and TX paths.

[0005] The invention seeks to provide a method permitting to avoid this drawback.

[0006] According to the invention, echo cancelling is performed by means of a hybrid which comprises tunable passive elements whereby the values of the tunable passive elements are adapted and controlled by digital control means.

[0007] The tuning is analog but the control is digital. As the adaptive echo cancelling is achieved before any digital processing, it improves, in contrast to digital echo cancelling, the signal-to-noise ratio of the received and transmitted signals, and remedies the aforementioned nonlinear distortion problems from the analog front end. The term “comprise” has to be interpreted here as being non limitative.

[0008] Preferably a scaling factor is used for the tunable passive elements, for instance to permit an implementation on an integrated circuit.

[0009] The adaptation of the passive elements comprise the evaluation of the TX return loss gain in the hybrid, whereby the digital control means goes through a loop of adaptation of the tunable passive elements when this gain differs from zero, until this zero value of the gain is obtained.

[0010] The device according to the invention and particularly suitable to perform the above mentioned method comprises:

[0011] a hybrid, integrated in the analog front end of the communication line system, said hybrid comprising tunable passive elements, the values of which are controllable, and

[0012] digital control means coupled to the hybrid for controlling the tunable passive elements.

[0013] The passive elements may be mounted on-chip thereby enabling a cost effective implementation of this device.

[0014] The hybrid may comprise a hybrid bridge and a current to voltage converter.

[0015] The hybrid bridge may comprise two identical branches, each containing two impedances in series, one being a tunable balance impedance.

[0016] The digital control means may comprise a microprocessor.

[0017] The invention will now be described by way of example and with reference to the accompanying drawings in which:

[0018]FIG. 1 shows a block diagram of the interface between the line and the terminals of a transmitting and receiving device in a communication line system;

[0019]FIG. 2 shows schematically the echo canceller from the interface of FIG. 1;

[0020]FIG. 3 shows more in detail the architecture of the echo canceller of FIG. 2.

[0021]FIG. 1 shows the interface between the two-wire line 1 with impedance Z_(li) of an ISDN or XDSL network, on the one hand, and the terminals T and R of a digital transmitting and receiving device 21, for instance from a modem, on the other hand.

[0022] This interface comprises essentially a line transformer 2 with a transformer ratio 1:n, connected to the four connection pins TX0, TX1, RX0 and RX1 of the front end 3, which front end 3 is connected to the terminals T and R of this digital transmitting and receiving device 21.

[0023] In this front end 3 is integrated an echo canceller including a hybrid 5 and a digital control means 4, for instance a microprocessor.

[0024] In the transmitting or sending direction (TX direction), a digital/analog converter 6, a filter 7 and a driver 8 are mounted before the hybrid 5, while in the receiving or RX direction, this hybrid 5 is followed by a programmable gain amplifier 9 assuring a constant output power, a filter 10 and an analog to digital converter 11. In the TX direction, the pins TX0 and TX1 are coupled to the transformer 2 via line termination resistors 12. These are protection resistors limiting the power dissipation in the hybrid and analog front end, and having the resistance value R_(t)/2n², wherein n is the above mentioned ratio of the transformer 2.

[0025] A typical resistance value of R_(t) is 50 Ohm.

[0026] The pins RX0 and RX1 are coupled to the transformer 2 via line termination resistors 12A having the same above mentioned resistance value.

[0027] As shown in FIG. 2, the hybrid 5, possibly implemented as an integrated circuit, is composed of a hybrid bridge 13 and a current to voltage converter 14.

[0028] The hybrid bridge 13 combines the TX paths 15 and 16 starting from the output terminals 15A and 16A of driver 8, and the RX paths 17 and 18 terminating at the input terminals 17A and 18A of the programmable gain amplifier 9, and connects these terminals 15A, 16A, 17A and 18A to connection pins TX0, TX1, RX1 and RX0 respectively.

[0029] This hybrid bridge 13 contains two identical branches 19 coupling terminals 15A and 16A at the output side of the driver 8 with the connection pins RX0 and RX1, each branch 19 containing two impedances in series: balance impedance Z_(b) and impedance Z₂.

[0030] The impedance Z₂ in one of the branches 19 is mounted between terminal 15A and the balance impedance Z_(b) in series, another terminal of this balance impedance being coupled to connection pin RX0.

[0031] The impedance Z₂ in the other branch 19 is mounted between terminal 16A and the balance impedance Z_(b) in series with it, another terminal of this balance impedance being coupled to connection pin RX1.

[0032] Impedances Z₂ and impedances Z_(b) comprise tunable passive elements such as resistors, capacitors or inductors, controllable by the microprocessor 4. How these elements are tuned will be discussed in a further paragraph.

[0033] Moreover, a scaling factor k is used for the values of the passive elements of the impedances Z₂ and Z_(b) in such a way that these impedances can then for instance be implemented on-chip. Values for this scaling factor are for example 100 or 1000.

[0034] As shown in detail in FIG. 3, each balance impedance Z_(b) comprises a tunable resistor R₀, and, in parallel with this, a series connection of a tunable resistor R₁ and a tunable capacitor C₁, and in parallel with this circuit another not necessarily tunable resistor R₃ which may be scaled to value 2 kR_(t)/2n², wherein k is said scaling factor. The value 2 kR_(t)/2n² corresponds to the value of the line termination resistors 12 and 12A discussed previously.

[0035] In one embodiment the tunable resistors R₀ and R₁ and the tunable capacitor C₁ consist of a number of small discrete resistors in series, resp. capacitors in parallel. Tuning takes place by the control register of the microprocessor 4 connecting or disconnecting small resistors or capacitors so permitting a discrete controlling of the resistance or capacitance value.

[0036] The other impedance Z₂ in each branch consists of a not necessarily tunable resistor R₂ having the same resistance value as the resistor R₃, which may thus also be scaled to value 2 kR_(t)/2n², in series with a tunable capacitor C₂. This capacitor compensates for the inductance of the transformer 2.

[0037] In one embodiment the tunable capacitor C₂ consists of a number of small discrete capacitors in parallel and the control register of the microprocessor 4 connects or disconnects small capacitors so permitting a discrete controlling or tuning of the capacitance.

[0038] The current to voltage converter 14 consists of an operational amplifier 20 and two tunable feedback impedances Z_(fb) which have each the same configuration as impedances Z_(b) and thus the same passive elements.

[0039] In order to have a hybrid gain independent from the setting or frequencies, the feedback impedances Z_(fb) Of the current to voltage converter 14 are also tuned to be equal to Z_(b) because in that case the current to voltage converter 14 acts as a differential amplifier with gain one.

[0040] The gain G_(rx), being the gain from the voltage V_(rx) between the pin connections RX0 and RX1, to the voltage V_(hyb) at the output of the current to voltage converter 14 can be written as:

G _(rx) =V _(hyb) /V _(rx), which is equivalent to:

G _(rx) =−Z _(fb) /Z _(b) which is one if Z _(fb) =Z _(b).

[0041] The hybrid bridge 13 works in both directions, transmission and reception.

[0042] In the transmission or TX direction, the hybrid bridge 13 receives a voltage signal V_(tx) from the TX driver 8 between terminals 15A and 16A of paths 15 and 16, and transmits it directly to the pins TX0 and TX1.

[0043] In the reception or RX direction, a voltage signal coming from line 1 is firstly transformed by the transformer 2 into a voltage between connection pins RX0 and RX1 as shown in FIG. 1.

[0044] The resulting current through impedance Z_(b) is converted to voltage V_(hyb) in the current to voltage converter 14.

[0045] The programmable gain amplifier (PGA) 9, is such that it compensates for the gain in the previous path, leading to a total gain G_(trx), this is the gain from V_(tr) to V_(hyb), being reduced to one. V_(tr) is the voltage over the equivalent line voltage source 21 in series with the equivalent impedance Z_(tr+li) of the line 1 and the transformer 2 in the equivalent circuit as indicated in dashed line in FIGS. 2 and 3 and V_(hyb) is the voltage at the output of the current to voltage converter 14.

[0046] The man skilled in the art knows that this total gain G_(trx) can be deduced as follows:

G _(trx) =V _(hyb) /V _(trx), this is:

G _(trx) =Z _(fb)*(R_(t)/2n ²)/[Z _(b)(R _(t)/2n ²)+R _(t)/2n ² +Z _(b))*Z _(tr+li)/2]

G _(trx) =Z _(fb) /Z _(b)*(R _(t)/2n ²)/(R _(t)/2n ² +Z _(tr+li)/2)

[0047] This gain G_(trx) is not influenced by the echo cancelling.

[0048] Because the hybrid bridge 13 is in fact a differential impedance bridge, it is known for the man skilled in the art that the best echo return loss is obtained when the bridge is in equilibrium.

[0049] When the bridge is in equilibrium, the TX return loss gain, denoted hereafter as G_(txrl), is equal to zero.

[0050] Consequently, during initialisation of the system this TX return loss gain is evaluated as will be described hereafter.

[0051] A person skilled in the art can easily deduce that the evaluation of the TX return loss gain G_(txrl), this is the gain from V_(tx) to V_(hyb) wherein V_(tx) is the known voltage applied to terminals 15A and 16A, can be obtained as follows:

[0052] TX return loss gain:

G _(txrl) =V _(hyb) /V _(tx)

G _(txrl) =Z _(fb) /Z ₂ *[Z ₂ −Z _(b)−(R _(t)/2n*(Z _(tr+li)+2Z _(b))/Z _(tr+li])

[0053] divided by

[Z ₂*((R _(t)/2n*(Z _(tr+li)+2Z _(b))/Z _(tr+li) +Z _(b))]

[0054] The TX return loss gain G_(txrl) is equal to zero when the following condition is fulfilled:

[0055] Zb must be equal to:

kZ _(tr+li)*(Z ₂ −R _(t)/2n ²)/(kZ _(tr+li)+2kR _(t)/2n ²)

[0056] where k is the scaling factor.

[0057] If k is chosen such that

Z ₂ −R _(t)/2n ² =k 2R _(t)/2n ² being equivalent to:

Z ₂=(2k+1)R _(t)/2n ², and

Z _(b) reduces to: Z _(b)=[1/kZ _(tr+li)+1/k(2R _(t)/2n ²)]⁻¹

[0058] The balance impedance Z_(b) should thus approximate as close as possible the combination of the scaled termination resistance value 2kR_(t)/2n² in parallel with the scaled line and transformer impedance value kZ_(tr+li). The hybrid bridge is then in equilibrium and, as already mentioned, gives the best echo return loss.

[0059] In practice, the hybrid TX return loss gain G_(txrl) is calculated by the microprocessor 4 from the digitalised value of the measured voltage V_(hyb) and the digitalised known value of V_(tx).

[0060] If the hybrid TX return loss gain G_(txrl) differs from zero, the microprocessor tunes the tunable passive elements in the hybrid 5 and goes through a loop of adaptation until the zero value is obtained. After the adaptation is finished, the tunable passive elements R₁, C₁ and C₂ have reached their optimal value.

[0061] For this adaptation loop a dedicated fitting algorithm is used, for example the known “steepest descent” algorithm. With this steepest descent algorithm, the microprocessor 4 changes successively the value of the different tunable passive elements with a positive and a negative increment, the influence of thereof on the voltage V_(hyb), is checked and the element is finaly changed in the sense resulting in a decrease of V_(hyb)/V_(tx). This is repeated until the voltage ratio V_(hyb)/V_(tx), this is the TX return loss gain G_(txrl), no longer decreases.

[0062] In one embodiment, particularly for xDSL applications, the resistor R₀ can be tuned between values of 28 and 896 kOhm, the resistor R₁ between values of 15 and 240 kOhm, the capacitor C₁ between values of 7.5 and 120 pF and the capacitor C₂ between values of 240 and 390 pF. 

1. Method for echo cancelling in a communication line system, characterised in that said method is performed by adapting tunable passive elements of a hybrid (5) which forms part of the analog front end of said communications line system, whereby the values of the tunable passive elements are controlled by digital control means (4).
 2. Method according to claim 1 , characterised in that a scaling factor (k) is used for adapting said tunable passive elements.
 3. Method according to claim 1 , characterised in that adapting said tunable passive elements comprises a step of measuring the TX return loss gain in said hybrid (5), whereby, when this gain differs from zero, the digital control means (4) goes through a loop of adaptation of the tunable passive elements until this zero value of said TX return loss gain is obtained.
 4. Method according to claims 2 and 3, characterised in that said hybrid (5) comprises a hybrid bridge (13) with two branches (19), each comprising two tunable passive impedances (Z₂ and Z_(b)) in series, one of which being a tunable balance impedance (Z_(b)), said tunable passive impedances being tuned such that the value of said tunable balance impedance (Z_(b)) approximates as close as possible the scaled impedance value of the parallel circuit of the line termination resistance (2R_(t)/2n²) in the TX paths, and the line impedance (Z_(tr+li)).
 5. Method according to claim 4 , characterised in that said hybrid (5) comprises a current to voltage converter (14), the feedback impedances (Z_(fb)) of which being adapted so as to be equal to said tunable balance impedance (Z_(b)).
 6. Device for echo cancelling in a communication line system, characterised in that it comprises: a hybrid (5), being part of the analog front end of said communication line system, said hybrid (5) comprising tunable passive elements, the values of which are controllable, by a digital control means (4) coupled to said hybrid (5) and also included in said device.
 7. Device according to claim 6 , characterised in that said tunable passive elements of said hybrid (5) are scalable by a predetermined scaling factor (k).
 8. Device according to claim 6 , characterised in that said hybrid (5) comprises a hybrid bridge (13) and a current to voltage converter (14).
 9. Device according to claim 8 , characterised in that said hybrid bridge (13) comprises two identical branches (19), each comprising a tunable balance impedance (Z_(b)) in series with a second tunable impedance (Z₂).
 10. Device according to claim 9 , characterised in that said tunable balance impedance (Z_(b)) comprises a tunable resistor (R₀), in parallel with a series connection of a tunable resistor (R₁) and a tunable capacitor (C₁), and in parallel with another resistor (R₃).
 11. Device according to claim 10 , characterised in that said another resistor (R₃) has the same resistance value (2kR_(t)/2n²), as the line termination resistors (12) in the TX paths, scaled with said scaling factor (k).
 12. Device according to claim 9 , characterised in that said second tunable impedance (Z₂) in each branch (19) comprises a resistor (R₂) in series with a tunable capacitor (C₂), the value (2kR_(t)/2n²) of said resistor (R₂) being the same as the resistance value of said line termination resistors (12) in the TX paths, scaled with said scaling factor (k).
 13. Device according to claim 9 , characterised in that said current to voltage converter (14) comprises an operational amplifier (20) with tunable feedback impedances (Z_(fb)) having the same impedance values as said tunable balance impedance (Z_(b)).
 14. Device according to claim 6 , characterised in that said digital control means comprises a microprocessor (4).
 15. Device according to claim 6 , characterised in that said tunable passive elements are part of an integrated circuit. 